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Method for dispersed FIFO memories in FPGA chips

IP.com Disclosure Number: IPCOM000074606D
Publication Date: 2005-Feb-23
Document File: 3 page(s) / 57K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for dispersed first in, first out (FIFO) memories in field programmable gate array (FPGA) chips. Benefits include improved performance.

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Method for dispersed FIFO memories in FPGA chips

Disclosed is a method for dispersed first in, first out (FIFO) memories in field programmable gate array (FPGA) chips. Benefits include improved performance.

Background

              FPGA chips are typically used when no appropriate application-specific integrated circuit (ASIC) is available on the market. In advanced telecom computing architecture (ATCA) boards, the FPGA chips are used as bus converters because the FPGA must contain a FIFO for buffering transmitted data. Most FPGA chips have a special block random access memory (RAM) storage element for implementing large memories (see Figure 1).

              A problem with using FPGA chips is that its block RAM is hard-placed. The required design can be created before the board schematic and the signals to the appropriate user input/output (I/O) are identified. However, this approach increases the time required to create the scheme. It also makes the design of the printed circuit board (PCB) layout difficult by not allowing pin locations to be easily changed. If the FPGA programmer enables pin swapping during PCB layout design, a long path occurs between the FIFO and the user I/O. The long paths increase setup and clock-to-output times (see Figure 2).

Description

              The disclosed method includes dispersed FIFO memories in FPGA chips. A very small FIFO is connected to the main FIFO, which is based on block RAM using distributed logic (see Figure 3).

              All critical...