Browse Prior Art Database

Bucket Bridge Delay Line with Loss Compensations

IP.com Disclosure Number: IPCOM000074609D
Original Publication Date: 1971-May-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Heller, LG: AUTHOR

Abstract

This electronic variable line for data storage or for data processing is a series of field-effect transistors, acting as charge transfer switches, coupled to a chain of incrementally increasing or decreasing storage capacitors, with each capacitor connected between the gate and drain of a respective transistor to compensate for either leakage current or incomplete transfer of information.

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Bucket Bridge Delay Line with Loss Compensations

This electronic variable line for data storage or for data processing is a series of field-effect transistors, acting as charge transfer switches, coupled to a chain of incrementally increasing or decreasing storage capacitors, with each capacitor connected between the gate and drain of a respective transistor to compensate for either leakage current or incomplete transfer of information.

Referring to the drawing, two identical square wave pulses 0 1 and 0 2, 180 degrees out of phase, with a frequency equal to a sampling frequency E1 are applied to lines 10 and 11, respectively. Line 10 is connected to the gate of every alternate transistor in the series; e.g., transistors T1 & T3, and to a charging capacitor T5, while line 11 is connected to the gate of the remaining transistors; e.g., transistors T2 & T4. Assuming that the circuit has been previously cycled until all the capacitors shown have been charged to a voltage one threshold voltage below the gate voltage and information has been written into capacitor C1 by deducting charge therefrom; then, when 0 1 is applied to T1 it switches on transistor T1 causing the information stored in capacitor C1 to be transferred to capacitor C2. When pulse 0 2 is applied to the gate of transistor T2, the information now stored in capacitor C2 is caused to be transferred to capacitor C3. Sequential application of the pulses to their respective transistors continues to transfer...