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Diagnostic Circuitry for Synchronous Communications Adapter

IP.com Disclosure Number: IPCOM000074616D
Original Publication Date: 1971-May-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 69K

Publishing Venue

IBM

Related People

Froemke, JW: AUTHOR

Abstract

This diagnostic circuitry provides a test loop within a synchronous communications adapter simulating the data set interface with which the adapter is used in ordinary operations for transmitting data on to a transmission line. It is, therefore, not necessary for testing the communications adapter hardware to go on line with a remote station.

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Diagnostic Circuitry for Synchronous Communications Adapter

This diagnostic circuitry provides a test loop within a synchronous communications adapter simulating the data set interface with which the adapter is used in ordinary operations for transmitting data on to a transmission line. It is, therefore, not necessary for testing the communications adapter hardware to go on line with a remote station.

Referring to Fig. 2, in ordinary operations, data from transmission line 10 passes through demodulator 12 and through external cable switch portion 14a, through CV (Voltage Converter) 16 and an OR circuit 18 to a received data line
20. Line 20 supplies the data through a receive trigger 22 (Fig. 1) to a shift register 24. The series of bits is assembled by the shift register and is ultimately transferred through a CPU Data Bus In 26 to the associated CPU. Data is transmitted onto a transmission line 38 from the shift register 24, which changes the data from a parallel byte of bits to a series of bits, and through data carry trigger 28, transmit trigger 30, transmitted data line 32, CV (Voltage Converter) 34, the portion 14b of the external cable switch, and a modulator 36, which together with the demodulator 12 forms a conventional modem 40. The adapter shown in Fig. 2 includes a request-to-send line 42 providing a signal normally sent to the modem 40 which responds when ready with the clear-to-send signal on line 44. The adapter when enabled, provides a data-terminal-ready signal on line 46, and the data-set-ready signal on line 48 indicates that the modem 40 is ready.

A test loop is established when the external cable switch parts 14a and 14b are moved out of their illustrated positions into upper positions. In these positions, signals are shunted around modem 40 and the transmitted-data signal 32 is supplied to received-data line 20, the request-to-send signal is connected to the clear-to-send line 44, and the data-terminal-ready signal is connected to the data-set-ready line 48. The lines 32 and 20 connect the receive trigger 22 with the transmit trigger 30, and signals are artificially supplied to the clear-to-send line 44 and the data-set-ready line 48, thus completing a test loop in which the hardware of the Fig. 1 adapter can be tested without the necessity...