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Processing Vectors as a Plurality of Segments

IP.com Disclosure Number: IPCOM000074663D
Original Publication Date: 1971-May-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 13K

IBM

Related People

Moss, LM: AUTHOR [+3]

Abstract

Disclosed is the treatment of vectors in a vector processor with vector registers, when the length of the vector exceeds the capacity of the registers. Vectors are described in main memory by a count of the number of elements (CT), the address of the first element (Bv), and the separation between elements (S). The segment of a vector that is currently in a register is described by specifying the register and by a length (L) associated with the register. The full length of the register could be other than a power of 2 but the arithmetic required becomes much harder and in this embodiment is 256 elements long. The technique comprises two parts: 1) Extended Count Control, and 2) Address Control.

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Processing Vectors as a Plurality of Segments

Disclosed is the treatment of vectors in a vector processor with vector registers, when the length of the vector exceeds the capacity of the registers. Vectors are described in main memory by a count of the number of elements (CT), the address of the first element (Bv), and the separation between elements
(S). The segment of a vector that is currently in a register is described by specifying the register and by a length (L) associated with the register. The full length of the register could be other than a power of 2 but the arithmetic required becomes much harder and in this embodiment is 256 elements long. The technique comprises two parts: 1) Extended Count Control, and 2) Address Control.

The embodiment requires a special count register, a count control mechanism, and an address control mechanism. The count register is a 64-bit register and is comprised of two halves, a Countdown Register (CTd) and a Countup Register (CTu).

It is apparent that it is desirable to segment calculations if the length of the vectors is over 256 elements. That is, many vector operations should be done for the first 256 elements. Then, the same vector operations should be repeated for the next 256 elements of each vector, and so forth, until the final segment is reached which may have less than 256 elements to process. In order to proceed with the calculation in this manner, it is necessary to identify the instructions which are to be processed for each segment. It is necessary for the first element addresses (Bv's) of all the vectors to be referenced in the block to be specified. The mechanism will automatically provide addressability to each segment (Bs) of the vectors, as required.

An instruction, Branch on Extended Count, is defined. I...