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Self Testing Partially Checked Decoder Checking Unit

IP.com Disclosure Number: IPCOM000074707D
Original Publication Date: 1971-May-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Carter, WC: AUTHOR [+3]

Abstract

A decoder is defined herein as any combinational circuit with n inputs and j outputs, 2/n-1/< j < 2/n/, where exactly one of the j outputs is activated by each of j n-variable input signal patterns. As described in the publication of W. C. Carter, W. C. Bouricius, D. C. Jessep, J. P. Roth, P. R. Schneider and A. B. Wadia, "A Theory of Design of Fault-Tolerant Computers Using Standby Sparing", 1971 International Symposium on Fault-Tolerant Computing, Pasadena, California, March 1-3, 1971, if the decoder is designed to produce invalid outputs for those inputs other than the j input patterns, such circuits may be checked by self-testing 1 out of j checking circuits.

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Self Testing Partially Checked Decoder Checking Unit

A decoder is defined herein as any combinational circuit with n inputs and j outputs, 2/n-1/< j < 2/n/, where exactly one of the j outputs is activated by each of j n-variable input signal patterns. As described in the publication of W. C. Carter,
W. C. Bouricius, D. C. Jessep, J. P. Roth, P. R. Schneider and A. B. Wadia, "A Theory of Design of Fault-Tolerant Computers Using Standby Sparing", 1971 International Symposium on Fault-Tolerant Computing, Pasadena, California, March 1-3, 1971, if the decoder is designed to produce invalid outputs for those inputs other than the j input patterns, such circuits may be checked by self- testing 1 out of j checking circuits. If the invalid input patterns produce even parity (an output of all zeros is usual), a self-testing parity check circuit can be used to detect all single failures immediately upon their producing an error, and save circuitry, as also described in the aforementioned publication. As shown in Table 1, for usual designs and circuit families, the decoder and checking circuit have more than twice the components of the original decoder.

However, many fewer circuits are used if the two output checking circuits are constructed as follows. The first checker output c(1) is the OR of all decoder outputs activated by input patterns with old parity. The second checker output c(2) is the OR of all decoder outputs activated by input patterns with even parity. Checker outputs (c(1), c(2)) of 01 or 10 signify correct operation, 00 or 11, erroneous operation. For a fan-in of two, a circuit comparison with parity checked decoders is shown in Table 1.

The disadvantage with this system is that all single failures are not immediately detected upon causing an error. For example, in a decoder constructed of AND gates, an output s-a-1 feeding c will be detected only when c is 1. However, all s-a-0 faults are immediately detected when causing an error.

The probability of failure detection is readily calculated for decoders constructed of AND gates and is unchanged for other implementations obtained by applying De Morgan's law,...