Browse Prior Art Database

Self Aligned Aluminum Gate FET Fabrication

IP.com Disclosure Number: IPCOM000074708D
Original Publication Date: 1971-May-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Elie, GT: AUTHOR [+2]

Abstract

A self-aligned aluminum gate FET fabrication technique that provides marked improvement in electrical performance which includes obtaining higher threshold voltage (V(t)), higher gain-band width product, and lower gate-source and gate-drain capacitance is shown in the drawings.

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Self Aligned Aluminum Gate FET Fabrication

A self-aligned aluminum gate FET fabrication technique that provides marked improvement in electrical performance which includes obtaining higher threshold voltage (V(t)), higher gain-band width product, and lower gate-source and gate-drain capacitance is shown in the drawings.

Fig. 1 shows a silicon substrate 11 having an initial oxide 12 which is thermally grown on the surface of substrate 11 to a thickness of approximately 6000 Angstroms. A source-gate-drain region is defined and etched using standard photolithographic and etching techniques. After etching, a thin oxide region 13 of approximately 500 Angstroms is regrown on the surface of substrate
11.

In Fig. 2, a layer of silicon nitride 14 of approximately 1500 Angstroms thickness is deposited over oxide regions 12, 13 and followed by the deposition of a layer 15 of pyrolytic silicon dioxide of approximately 2000 Angstrom thickness. Layer 15 is used as an etching mask for the silicon nitride layer 14. Silicon nitride layer 14 functions both as an impurity diffusion mask and as an oxidation mask; the latter function preventing further growth of thin oxide layer 13 in the gate region.

In Fig. 3, source and drain diffusion apertures 16 and 17 are delineated in the silicon nitride layer 14 using portions of layer 15 as a mask for the silicon nitride.

In Fig. 4, portions of thin oxide region 13 not covered with portions of silicon nitride layer 14 are removed completing apertures 16 and 17 and exposing surface portions of substrate 11. At this point, any remaining portions of silicon dioxide lay...