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Error Checking by Pseuduplication

IP.com Disclosure Number: IPCOM000074716D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 30K

Publishing Venue

IBM

Related People

Anello, AJ: AUTHOR [+5]

Abstract

This description is directed to the detection of errors within computer systems, and particularly errors occurring in arithmetic and logical operations performed by computing apparatus in the computer.

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Error Checking by Pseuduplication

This description is directed to the detection of errors within computer systems, and particularly errors occurring in arithmetic and logical operations performed by computing apparatus in the computer.

This error detection arrangement employs a technique which can be called pseudoduplication, in which the errors are detected in a manner somewhat similar to the duplication of hardware technique. An electronic representation of an answer for a given arithmetic or logical operation is developed and is stored in a register. The arithmetic or logical operation is performed a second time, although the performing of the second operation requires the use of a different data path through the same arithmetic and logic unit for each of the input data bits. If the electronic circuitry is working properly, the results of the first operation and that of the second operation using different data paths will be identical. A simple Exclusive OR circuit for each bit position is all that is required to detect the presence of an error, as indicated by a difference between the first generated answer and the second generated answer for the given arithmetic or logical operation.

The figure shows an application of this error detection process. ALU 5 is an arithmetic-logical unit which is capable of performing various types of arithmetic and logical operations upon the data entering the ALU.

A simple example of the operation is to consider the performing of and OR operation upon the data contained in A Register 1 and the data in B Register 2. In the first phase or mode of the operation, the data in A Register 1 is gated directly to ALU 5 as is the data in B Register 2. The data enters the ALU 5 where the OR operation is performed. The output of ALU 5 represents the data that should result from an OR operation upon the given binary data contained within A Register 1 and B Register 2. This data leaving ALU 5 is gated through gating circuitry 6 to C Register 7. In order to determine whether the contents of the C Register 7 represent a correct result, a second OR operation is performed. The second phase of the operation takes the data in...