Browse Prior Art Database

Gated Clock with Phase Locked Restart

IP.com Disclosure Number: IPCOM000074725D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Fangmeier, L: AUTHOR [+3]

Abstract

A continuous pulse generator, a system clock for example, is suspended without slivering pulses and restarted in the suspended phase. The suspension may be either immediate or upon normal pulse termination.

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Gated Clock with Phase Locked Restart

A continuous pulse generator, a system clock for example, is suspended without slivering pulses and restarted in the suspended phase. The suspension may be either immediate or upon normal pulse termination.

With a start signal applied, the OR-delay feedback loop generates a series of signals which appear as output pulses from the pulse-dividing trigger TB. The output repetition rate is one-half the reciprocal of all loop delays.

When the start signal is replaced by a stop signal, both triggers are reset immediately terminating the output pulse series. Trigger TB stores the value of the terminated pulse and restarts the series with a pulse, having the stored value, upon replacement of the stop signal with a start signal.

In an alternative version, the stop signal terminates the output pulse series upon the end of the current pulse. As shown by the dashed lines, the trigger TA is reset by the stop signal only after the output falls.

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