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Di-Istor Shift Register

IP.com Disclosure Number: IPCOM000074750D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Cannistra, AT: AUTHOR [+4]

Abstract

A Di-Istor shift register loads a series of SCR storage cells S1, S2, S3... for use as a Writable Personalized Chip. The Di-Istors are loaded as follows: The phase line is brought to +V charging the capacitor C to +V - V(D) where V(D) = Voltage drop across diode D.

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Di-Istor Shift Register

A Di-Istor shift register loads a series of SCR storage cells S1, S2, S3... for use as a Writable Personalized Chip. The Di-Istors are loaded as follows: The phase line is brought to +V charging the capacitor C to +V - V(D) where V(D) = Voltage drop across diode D.

The phase line phi N is brought to ground. If the input is in its high voltage state (+V - V(D)), the transistor base-emitter junction is forward biased. The capacitor will be discharged leaving it in its low voltage state. If the input is in its low voltage state, the base-emitter junction will not be forward biased and the capacitor will not be discharged.

The phase drivers are sequenced phi 1, phi 2, phi 3, phi 4 (Fig. B). On the initial cycles, phase 1, 2 and 3 will shift no significant data. On the second cycle phase 1 and 2 will shift no significant data. After the third cycle, each operation of the phase drivers will shift at least one bit of significant data.

After the required data is stored in the shift register, the SCR's can be loaded. During the shift register load operation, the SCR load control line is biased to +V, thereby back biasing the input junction. To load the SCR, the SCR control line is grounded. In grounding the control line, the input junction of the SCR is forwarded biased if its associated Di-Istor capacitor has a positive charge. This will turn on and latch the SCR storing the data formerly loaded in the Di-Istor. On grounding the control line, thos...