Browse Prior Art Database

FET Gate Structure

IP.com Disclosure Number: IPCOM000074764D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Garnache, RR: AUTHOR [+2]

Abstract

This method provides a non-self-aligned, self-passivating silicon gate structure useful in charge storage type memory cells.

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FET Gate Structure

This method provides a non-self-aligned, self-passivating silicon gate structure useful in charge storage type memory cells.

Initial thermal oxide 1 is grown on semiconductor wafer 2, source 3 and drain 4 are defined, diffused and driven in. Thick oxide 1 is then stripped from the device area and clean thermal oxide 5 is grown. This is followed by silicon nitride layer 6 and poly-silicon layer 7 grown in the same deposition chamber to avoid contamination of the gate metal/oxide interface. A photoetch process is used to etch through poly-silicon 7 which then forms an etch mask for silicon nitride layer 6 Contact holes are opened in the same manner using buffered HF. The entire wafer is then covered with aluminum 8 which is subtractively etched to form the metallization pattern. Excess poly-silicon 7 not underlying aluminum layer 8 is then removed. The wafer is annealed at a suitable temperature to form ohmic contacts in source and drain areas 3 and 4, and also to drive aluminum into poly- silicon 7 to provide suitable doping to render the silicon gate conductive.

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