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Delay Line Clock Data Separator

IP.com Disclosure Number: IPCOM000074769D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Hahs, WR: AUTHOR

Abstract

This circuit separates clock and data pulses transmitted at double frequency. The circuit accommodates variations of +/- 25% without the need for a memory section or a clock pulse generator in the receiver. The system features the use of delay lines to generate a variable data window. For every clock pulse that is introduced into the circuit, a gating pulse is generated to strobe in the data pulse. The system resets itself by delay line time-out to accept the next clock pulse, allowing the system to recover even if there is a loss of raw data. The system is completely resynchronized on the first clock and no data sequence.

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Delay Line Clock Data Separator

This circuit separates clock and data pulses transmitted at double frequency. The circuit accommodates variations of +/- 25% without the need for a memory section or a clock pulse generator in the receiver. The system features the use of delay lines to generate a variable data window. For every clock pulse that is introduced into the circuit, a gating pulse is generated to strobe in the data pulse. The system resets itself by delay line time-out to accept the next clock pulse, allowing the system to recover even if there is a loss of raw data. The system is completely resynchronized on the first clock and no data sequence.

The raw data from read amplifier and shaping circuits, not shown, at 1 is fed to pulse former and start circuit 2. The pulse former is a 50 nanosecond delay line network which fixes the pulse width into the system. The read gate signal in the start circuit eliminates the possibility of a pulse of less than 50 nanoseconds activating the circuit. The unseparated clock and data pulses from pulse former 2 is fed to clock AND gate 4. AND gate 4 and data AND gate 6 form a double AND gate for discriminating between the clock and data pulses. Binary trigger 8 receives the pulses from clock AND gate 4. The output of trigger 8 is input to tapped delay lines 10. Signals at given delay intervals are tapped off the delay lines to create odd-even timing at odd and even gates 12 and 13, respectively. The odd and even timing pul...