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Masking Technique for Control of an Associative Parallel Processor

IP.com Disclosure Number: IPCOM000074774D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Mommens, JH: AUTHOR [+2]

Abstract

This is an associative processor to be used as a programmable auxiliary processor to assist a conventional main processor in special problems.

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Masking Technique for Control of an Associative Parallel Processor

This is an associative processor to be used as a programmable auxiliary processor to assist a conventional main processor in special problems.

Programs are loaded from the main processor, not shown, and are used to load data, to process it, and to return results to the main processor. The main processor has at all times the ability to force the auxiliary processor to accept a new program or to branch to a specified location in its program. Simplicity of implementation is achieved by the use of standard modular units with a minimum of additional special logic. Generality of application is achieved by implementing many control functions in memory, and by the inclusion of some extra associative memory features which are not necessarily required in all applications.

Referring to Fig. A, the processor is shown as consisting of two main components: an associative functional memory 10 and a read/write control store
12. The associative memory is used to store both data being processed and control information in the form of counts, field definitions, useful constants and masking data. The control information is stored in the control portion 14 of the associative memory array 10.

Control sequences for the execution of a program are contained in a read/write control store 12 normally operating in a read-only mode. Conditional branches in the program are made by testing the condition of various signals in the processor and its I/O interfaces.

Program loading, i.e., writing into the control store, is performed under the control of a short, permanent, initial load program.

Input and output data transfers are made by way of the associative array bit control unit 16. Basic interface control is carried out by the control store 12 which can generate and test outgoing and incoming control signals; if a more complex I/O control is used, then the addition of an interface control unit is required.

Referring now to Fig. B, there is shown the masking technique utilized for control of the associative processor. Conventional associative parallel processors require complicated control systems for manipulating both mask and data registers and for providing counting facilities for definition of data fields. This particular technique implements the control within the associative memory array.

In order to introduce the control mask to the associative memory arrays 10 and 14, two instructions are required, a READ MASK and a WRITE MASK. Both of these instructions permit mask information to be stored and processed in the array in the same manner as if they were ordinary data. Note, that since the associative memory array contains both data and control mask information, the ratio of data and control words can be tailored to any given problem. That is, there is no fixed restraint on the boundaries of the control mask or the data. A further advantage which is obtained by this particular organization,...