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Browse Prior Art Database

Decoding Gate Voltage Switch

IP.com Disclosure Number: IPCOM000074810D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Blount, FT: AUTHOR [+4]

Abstract

A monolithic memory integrated circuit preferably is subjected to two power levels, that is a low-power level when the memory array is in the nonselected or inactive state and a higher level of power for reading and writing into the memory. Shown is a circuit for placing the monolithic memory circuit in its high-power state.

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Decoding Gate Voltage Switch

A monolithic memory integrated circuit preferably is subjected to two power levels, that is a low-power level when the memory array is in the nonselected or inactive state and a higher level of power for reading and writing into the memory. Shown is a circuit for placing the monolithic memory circuit in its high- power state.

The circuit does a one or two decode using a choice of voltage gates Vg1 or Vg2 for the address. The circuit operation is as follows. During full select time, the timing pulse TP is down and either voltage gates Vgl or Vg2 is up. Transistors T5 and T6 are off. If voltage gate Vg1 is up, transistor T1 is on. Output A1 provides voltage for a first group of word driver circuits. Output AC provides all common line circuits. If voltage gate Vg2 is up, transistor T4 is on and output A2 provides voltage to a second group of word drivers. Output AC is on in either case.

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