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Reducing FET Channel Cross Section

IP.com Disclosure Number: IPCOM000074824D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Fischer, W: AUTHOR

Abstract

The impedance of an IGFET device is proportional to the ratio L/W of the channel length L to the channel width W. Minimum W ultimately is determined by the minimum line width which can be reproduced photolithography. Further reduction in W would facilitate a significant reduction in L for a given desired channel impedance with commensurate substantial space saving. This can be accomplished by the introduction of an extra diffusion step which effectively reduces FET channel cross section beyond the limitations of photolithographic techniques.

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Reducing FET Channel Cross Section

The impedance of an IGFET device is proportional to the ratio L/W of the channel length L to the channel width W. Minimum W ultimately is determined by the minimum line width which can be reproduced photolithography. Further reduction in W would facilitate a significant reduction in L for a given desired channel impedance with commensurate substantial space saving. This can be accomplished by the introduction of an extra diffusion step which effectively reduces FET channel cross section beyond the limitations of photolithographic techniques.

Drawing A shows the channel cross section of a conventional IGFET device. Assuming a minimum masking line width Wm for etching away the thick oxide in the channel area and defining the channel width, unavoidable oxide undercutting during the etching process results in the actual width W indicated. Letting Delta Ox represent oxide undercutting, actual channel width W equals Wm + 2 Delta Ox.

In drawing B, the same minimum line width is assumed for making a photoresist mask which, in turn, is used for etching away oxide. This time, however, the oxide mask is removed in the nonchannel area but retained in region 1 for making the P+ diffusion in regions 2 and 3 on either side of the IGFET device channel. In the illustrative case, the IGFET is an N channel device on P- substrate 4. In transferring the minimum line width pattern from the photoresist, not shown, to oxide mask 1, the oxide undercutti...