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Auto Range Control for Analog To Digital Converter

IP.com Disclosure Number: IPCOM000074833D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Arnold, FJ: AUTHOR [+3]

Abstract

This system provides high-speed, automatic ranging of an analog-to-digital converter for optimum resolution of an analog input, by scanning through a number of distinct stages of amplification and logically choosing the highest level of amplification to best resolve the analog input. Optimum resolution occurs at the highest gain which does not exceed the conversion range of the ADC.

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Auto Range Control for Analog To Digital Converter

This system provides high-speed, automatic ranging of an analog-to-digital converter for optimum resolution of an analog input, by scanning through a number of distinct stages of amplification and logically choosing the highest level of amplification to best resolve the analog input. Optimum resolution occurs at the highest gain which does not exceed the conversion range of the ADC.

The ADC is, for example, a commercially available type having a 12-bit digital output, with an 8-channel, multiplexed input, only five of the input channels being used, as indicated schematically at A. Exceeding the high end of the conversion range results in all "1" bits. Besides the 12-bit digital output, there is a 3-bit output designating the channel that was accessed. The 8-input channels are coded 0-7. Three other signals are available, (1) BUSY, which rises when digitizing begins and falls when valid data appears at the output, (2) START, which initiates the digitizing process, and (3) RESET, which will be explained below.

There are two other features of the ADC that are essential to the described implementation. One mode of ADC operations is the "short-cycled channel sequenced" operation. In this mode, only X number of the available channels are used. For example, in the particular application, the ADC is "short-cycled" only for channels 0 through 5. With every "START" pulse, a reading is taken on the next successive channel.

The other feature is "RESET". When this line is activated, the multiplexor returns to channel 0, from whichever channel it had just taken a reading on. In this particular application, channel 0 is a home position. There is no input, and no reading will be taken on it. Five stages of overlapping amplification are used, as shown at B. The highest to lowest stages of amplification are connected to channels 1 through 5, respectively. Gains were chosen for a full scale reading with the following inputs: 512mv, 128mv, 32mv, 8mv, and 2mv.

A typical read operation is as follows: (1) Assume that a valid input occurs on channel 2, i.e., this stage of amplification is the first that does not exceed the high end of the con...