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System Relocation Method

IP.com Disclosure Number: IPCOM000074840D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 4 page(s) / 42K

Publishing Venue

IBM

Related People

James, RS: AUTHOR [+3]

Abstract

Dynamic Storage Oriented Relocation (DSOR) provides a two-level table look-up using hardware tables, but in a simplified manner that minimizes hardware costs and allows fast translation. The address translation method and hardware tables of DSOR are shown in Fig. 1.

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System Relocation Method

Dynamic Storage Oriented Relocation (DSOR) provides a two-level table look-up using hardware tables, but in a simplified manner that minimizes hardware costs and allows fast translation. The address translation method and hardware tables of DSOR are shown in Fig. 1.

Each storage requestor (user) has a unique identification (ID) 10 and always sends the ID with the requested address. If the system has a small number of users, the ID field and ID paths in the system may be quite small. Likewise, for large numbers of users or multiple ID's per user, the ID field and ID paths will be large. The use of an ID allows each user to have a virtual address space that may be as large as the maximum addressing capability of the system (24 or 31 bits, for example.)

A user, (CPU, channel) sends an address and ID to a translate unit. The ID addresses a certain row in the column table 12 and a specific entry (segment) in the chosen row is selected by the segment number 14. The segment number is the high-order bits of the address. The selected-column table-entry contains the number of the column to be selected in the page table 16, as well as a valid bit, not shown.

The page table is accessed only if the valid bit in the column table is on. A segment exception condition is generated if the valid bit is off.

The contents 18 of the selected column table entry are used to select the proper column in the page table. The page portion 20 of the address is used to select the proper row in the page table. The contents 22 of the selected position (row and column have been determined) of the page table are the high-order address-bits of the physical storage location to be referenced, as well as a page- valid bit. The particular byte addressed in the referenced page is located by the displacement field 24 of the address (the low-order bits). If the page-valid bit is off, a page exception condition will be flagged.

No add functions are required for the translation process. Because no additions are required, the contents of the column table are used to address the page table as soon as the column-table storage-output is valid, and the page table contents are used to access main storage as soon as the page-table storage output is valid. Using presently available monolithic storage cards, the translation process takes approximately two monolithic-storage cycle times, which results in a very small addition to the physical (main) storage access time, assuming that the physical storage cycle time is significantly slower than the monolithic storage cycle time (usually the case). Processors that have a cache only use the translation mechanism when data is not found in the cache, or when data must be placed in main storage from the cache. By invalidating the cache when the ID changes, only virtual addressing is necessary for operation of the cache. The ID and address for each channel store must be compared with valid cache entries and any matchi...