Browse Prior Art Database

Compressed Partitioned Arrays

IP.com Disclosure Number: IPCOM000074845D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR

Abstract

In a logic array, a technique for minimizing the number of chips employed in a partitioned memory array while retaining needed functional capability.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 1

Compressed Partitioned Arrays

In a logic array, a technique for minimizing the number of chips employed in a partitioned memory array while retaining needed functional capability.

In partitioned arrays, the logic function generated depends upon the subfunctions of the individual partitions which, in turn, are a function of the inputs. In general, the desired function consists of a sum (OR) of the product of the subfunctions where some of the subfunctions are logically equal to one; therefore, these subfunctions may be considered as independent of their respective inputs and consequently, may be deleted from the array. This concept is basic to compressing the array, however, if all such subfunctions are deleted, some physical change such as altering the standard interconnections within the array would have to be made with each logic application, thus causing the obliteration of a basic advantage in logic arrays, i.e., standardized hardware. However, by analyzing the frequency distribution of subfunction use in an array for a variety of logic applications, a distribution of subfunctions per bit position can be arranged to assure one array type for several logic applications. Flexibility in achieving the distribution is available by logic modification, assignment of inputs to partitions, assignment of output functions to output bit positions, etc.

1