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Semidirect Access Shift Register Memory

IP.com Disclosure Number: IPCOM000074847D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Cain, RG: AUTHOR

Abstract

Given a processor which is limited, for example to 24 bits of addressing, implementation of the following mechanism could expedite provision of a memory capacity much higher than 2/24/.

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Semidirect Access Shift Register Memory

Given a processor which is limited, for example to 24 bits of addressing, implementation of the following mechanism could expedite provision of a memory capacity much higher than 2/24/.

Each bit in the memory is a static shift register of any length from 1 to 2/31/ and each shift register has external accessibility of exactly one bit position. Also provided is an instruction called the ROLL instruction having the following RS format OP R1 R2 B3 D3.

The address formed by adding bits 8-31 of register B3 to the D3 field of the instruction specifies a base address, B4, for the ROLL instruction. Bits 8-31 of the general purpose register specified by R2 are interpreted as a displacement D4, for the instruction. The positive storage, Real Storage range between B4 and B4 + D4 is defined as the ROLL REGION. The Roll Region is allowed to wrap from 2/24/-1 to 0. Bits 0-31 of the general purpose register specified by R1 define a roll count. At instruction execution time, the shift register for each bit within the roll region is shifted the number of bits specified by the roll count. This shift can be in either the positive or the negative direction depending on the sign of R1. The shift accomplishes the function of presenting a new bit position for external access. Shifting is performed modulo N, where N is the number of bit positions within the shift register.

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