Browse Prior Art Database

Self Registered Si Electrode FET

IP.com Disclosure Number: IPCOM000074865D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Chou, NJ: AUTHOR

Abstract

This is a method for fabricating FET structures by ion implantation, wherein a silicon gate electrode is used.

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Self Registered Si Electrode FET

This is a method for fabricating FET structures by ion implantation, wherein a silicon gate electrode is used.

In Fig. A, a silicon substrate has an SiO(2) layer on its top surface, the SiO(2) having apertures 1 therein. Deposited over the SiO(2) layer is a thin film 2 of silicon, which is to be the gate material. After deposition of silicon gate 2, ions are implanted into the device to form the source S and drain D regions, and to degenerately dope silicon gate electrodes 2. Because the silicon electrode is formed before ion implantation of the source and drain regions, there will be self- alignment of the gate with the source and drain regions.

In Fig. B, contacts are made to the source and drain regions and to the gate electrode. These contacts are shown schematically as wires 3.

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