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Schottky Barrier Read Only Memory

IP.com Disclosure Number: IPCOM000074867D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Gaensslen, FH: AUTHOR

Abstract

Described is a Schottky barrier diode read-only memory array. A schematic of such a circuit is shown in Fig. A. A top view of the layout of such a circuit is shown in Fig. B. Vertical lines 1 are diffused lines which are of N conductivity type. Lines 1 are made, as shown in Fig. C, by the outdiffusion of heavily doped buried N+ regions 2 through a P-type epitaxial layer 3. The surface concentration has to be low enough in order to get the needed diode breakdown voltage for a semiconductor-metal contact. Before outdiffusion, N+ regions 2 are diffused into P-type substrate 4. Also shown in Fig. A are horizontal lines 5 which are made of metal.

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Schottky Barrier Read Only Memory

Described is a Schottky barrier diode read-only memory array. A schematic of such a circuit is shown in Fig. A. A top view of the layout of such a circuit is shown in Fig. B. Vertical lines 1 are diffused lines which are of N conductivity type. Lines 1 are made, as shown in Fig. C, by the outdiffusion of heavily doped buried N+ regions 2 through a P-type epitaxial layer 3. The surface concentration has to be low enough in order to get the needed diode breakdown voltage for a semiconductor-metal contact. Before outdiffusion, N+ regions 2 are diffused into P-type substrate 4. Also shown in Fig. A are horizontal lines 5 which are made of metal. At every intersection, the metal of horizontal lines 5 either extends or does not extend into apertures 6 in oxide layer 7, depending on whether a binary 1 or a binary 0 is to be stored there. Fig. C shows a cross- sectional view taken along lines C-C in Fig. B. Metal lines 5 may be word lines, because the word line carries n units of current if the word length is n bits. The array is personalized during the final subtractive metal etching process. Because of this, wafers may be processed up to the personalization step, stored and then etched to personalize as desired.

A single-ended bit line approach is shown, but a double-ended design is also possible. When two bit lines are needed per bit, the overall density is cut in half. The obtainable bit density in this kind of memory is very high. I...