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Insulated Gate Field Effect Transistor

IP.com Disclosure Number: IPCOM000074868D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 3 page(s) / 34K

Publishing Venue

IBM

Related People

Yu, HN: AUTHOR

Abstract

Described is an insulated gate field-effect transistor, the source and drain contacts of which are formed with metal semiconductor Schottky barrier junctions instead of the usual PN junctions. In such arrangements, the conducting channel is normally blocked by the Schottky barrier. When negative potentials are applied to the gate with respect to the source, surface inversion lowers or eliminates the barriers so that conduction between drain and source is established. Fig. A shows a field-effect transistor 1, incorporating Schottky barrier source and drain contacts 2, 3, respectively, forming a metal-semiconductor interface with a semi-conductor substrate 4 of silicon or other suitable semiconductor.

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Insulated Gate Field Effect Transistor

Described is an insulated gate field-effect transistor, the source and drain contacts of which are formed with metal semiconductor Schottky barrier junctions instead of the usual PN junctions. In such arrangements, the conducting channel is normally blocked by the Schottky barrier. When negative potentials are applied to the gate with respect to the source, surface inversion lowers or eliminates the barriers so that conduction between drain and source is established. Fig. A shows a field-effect transistor 1, incorporating Schottky barrier source and drain contacts 2, 3, respectively, forming a metal-semiconductor interface with a semi- conductor substrate 4 of silicon or other suitable semiconductor. A gate electrode 5 is spaced from and disposed over a channel region between the Schottky barrier metallurgy 2 and 3 by gate insulation 6. Source and drain metallizations 7 and 8, respectively, are applied to the Schottky barriers 2, 3, respectively.

A typical fabrication process with silicon, which includes a self-aligned gate structure with very small overlap or feedback capacitance from the drain to the gate is described in what follows:

Fig. B shows an N-conductivity type substrate 4 of silicon, a surface portion of which is covered with a thermally grown thin gate oxide 6 and other portions of which are shown covered with a previously grown layer of silicon dioxide 11. Gate oxide 6 is thermally formed after delineating a gate opening using well- known photolithographic and etching techniques. Fig. C shows a gate electrode 5 formed from molybdenum or other refractory metals, semiconductors, and intermetallic compounds such as silicides of palladium, platinum, nickel, molybdenum, etc. spaced from the surface of substrate 4 by thin gate oxide region 6. Gate electrode 5 is formed by well-known photolithographic and etching techniques after de...