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Bilevel Powered FET Memory Cell

IP.com Disclosure Number: IPCOM000074874D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Palfi, TL: AUTHOR

Abstract

This memory cell has low-power requirements, high-packaging density and manufacturing yields.

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Bilevel Powered FET Memory Cell

This memory cell has low-power requirements, high-packaging density and manufacturing yields.

FET's 1 and 2 are cross-coupled bistable devices with FET's 3 and 4 as drain loads. 3 and 4 have higher impedances (5:1) than 1 and 2, which causes the circuit to be bistable. The impedance of 3 and 4, whichever is conducting, is determined by the gate voltage and the voltage drop across the associated bistable device. Since the current in the offside devices. e.g., 1 and 3, is zero, the gate voltage of the ON bistable device, i.e., 2, is equal to the gate voltage of the load devices 3 and 4. This condition results in a voltage divider proportional to the impedance of the bistable devices and their loads, or their width-to-length ratio. As long as this voltage is below the threshold of the OFF bistable device, the cell maintains its state. However, the voltage on the ON load drain should be equal or greater than its gate voltage.

When the word driver circuit is operated at a low level, the on-side devices 2 and 4 impedances will be increased proportionally, so that low-cell current is required without effecting bistability. Since the cell current is very sensitive to word line voltage variations, a feedback operational amplifier, not shown, can be utilized to give required regulation. The bits/sense lines have small effect on the cell currents and so they are connected to load devices 3 and 4. The current to the load devices is set by the...