Browse Prior Art Database

Input/Output Module

IP.com Disclosure Number: IPCOM000074876D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 5 page(s) / 55K

Publishing Venue

IBM

Related People

Annunziata, EJ: AUTHOR [+5]

Abstract

This input/output controller is a high-performance multichannel I/O module (IOM) designed to interface the processor and bus modules of other systems with input/output (I/O) devices. It provides the means of controlling and transferring information into and out of the processor.

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Input/Output Module

This input/output controller is a high-performance multichannel I/O module (IOM) designed to interface the processor and bus modules of other systems with input/output (I/O) devices. It provides the means of controlling and transferring information into and out of the processor.

The IOM is comprised of three main elements, the input/output transmitter 10, the input/output controller 12, and channels 14. In operation, these channels function as logically independent units. Software maintainability is provided through the use of a separate maintenance interface 16 to a maintenance processor. The IOM operates with several different types of data channels, such as high speed channels (HSC), medium speed channels (MSC) and byte multiplex channels (MPLX).

The IOM uses a single clock pulse per cycle which is furnished by the main processor and therefore runs at a rate determined by the processor.

The channel distributor 20 is the interface between the I/O controller and the channel. It provides temporary storage, timing pulses and a first level of priority determination among the various channels. All data and control information between the channel and the I/O controller funnel through the channel distributor.

The cable terminating unit 22 provides physical and electrical termination of the signal cables from both the I/O devices and the channels.

The bus interface 18 carries data and control information between the I/O controller and the storage bus. Each channel of the controller is instructed by the processor to commence an operation. An operation resulting from such an instruction involves a sequence or list of commands to a particular device. After being instructed, the controller obtains commands for each channel or subchannel and transmits data to or from main storage until the respective I/O operations are completed.

The IOM shares the storage bus with the processor. Storage access transactions are "pipelined" to the storage bus, that is, they occur on every machine cycle without demand-response interlocks across the storage bus interface.

Input/output operations are initiated and controlled by instructions, commands and control orders. These operations are consistent with IBM System/360 Principles of Operation (Form #822-6821). The processor program initiates an I/O operation by means of the start I/O instruction. This instruction identifies the channel and the I/O device to which the instruction is directed. It causes the controller to fetch a channel address word (CAW) from main storage. The CAW identifies the location in main storage at which the channel program associated with the instruction is stored, in the form of channel command words (CCWs) for the channel. The I/O transmitter examines the state of the subchannel, which is necessary to sustain the I/O operation corresponding to the specified device. As a result, the I/O transmitter indicates instruction acceptance or rejection by releasing the proc...