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Via Hole Etch Process and Control

IP.com Disclosure Number: IPCOM000074877D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-23
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Chang, K: AUTHOR [+2]

Abstract

In etching curvilinear via-holes through insulative layers of sputtered SiO to metal lands on a silicon wafer 1, a double-resist masking technique is employed to insure against mask defects or random pinholes. To facilitate alignment of the masks, the openings 2 in the second mask 3 are made slightly larger than the openings 4 in the first mask 5. In order to achieve uniform etching of all of the via holes 10, the openings 2 in the second mask 3 are made rectilinear. A double resist layer 12 is thereby produced having rectilinear holes 13 in the top portion and circular holes 14 in the lower portion. This minimizes surface tension problems during photoresist developing processing, which causes nonuniform etching where masks with curvilinear openings are used.

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Via Hole Etch Process and Control

In etching curvilinear via-holes through insulative layers of sputtered SiO to metal lands on a silicon wafer 1, a double-resist masking technique is employed to insure against mask defects or random pinholes. To facilitate alignment of the masks, the openings 2 in the second mask 3 are made slightly larger than the openings 4 in the first mask 5. In order to achieve uniform etching of all of the via holes 10, the openings 2 in the second mask 3 are made rectilinear. A double resist layer 12 is thereby produced having rectilinear holes 13 in the top portion and circular holes 14 in the lower portion. This minimizes surface tension problems during photoresist developing processing, which causes nonuniform etching where masks with curvilinear openings are used.

The completion of the removal of the sputtered SiO(2) from the via holes 10 to expose the aluminum metal land layer underneath the insulating layer is monitored by providing the emitter mask 6 and via-hole etch masks 3 and 5 with control holes 7, 8 and 9, respectively. These control holes are located in the waste portion of the wafer, which has no metal land but an SiO(2)-silicon interface. The reaching of this interface by the etch is visually apparent from the color difference at 11, between SiO(2) and silicon, at which time a slight theoretical over-etch of the via holes should have been accomplished.

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