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Regenerative Controlled Decay Storage Cell

IP.com Disclosure Number: IPCOM000074878D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Klepp, H: AUTHOR [+2]

Abstract

This storage cell includes cross-coupled transistors T1 and T2 nonlinearly loaded by diodes D1 and D2 and controlled erase diodes D3 and D4. Sensing resistors R1 and R2 are external to the basic cell.

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Regenerative Controlled Decay Storage Cell

This storage cell includes cross-coupled transistors T1 and T2 nonlinearly loaded by diodes D1 and D2 and controlled erase diodes D3 and D4. Sensing resistors R1 and R2 are external to the basic cell.

In operation, a data input in the form of a positive pulse is received from a high-impedance source into the base of T2. Such a high-impedance source might be a photosensitive diode. A positive signal at the base of T2 renders T2 conductive turning T1 off. This causes sense output B to have a more negative output and sense output A to have a more positive output (substantially near ground level), arbitrarily defining a "1". Conversely, a negative input to transistor T2 turns T2 off, thereby turning T1 on, causing sense output A to have a more negative level with output B having a more positive level (substantially potential
V), thereby arbitrarily defining a "0". In order to sense the output, a negative- going interrogate signal is applied to the emitters of T1 and T2 causing current to flow in the on transistor (either T1 or T2). The information is stored in the base- collector capacitance of T1 and T2 and remains there without power as long as there is a periodic (e.g. millisecond) interrogation of the cell. In the event it is desired to increase the write-read cycle of the cell, diodes D3 and D4 perform an erase function. A negative pulse applied to diodes D3 and D4 will pull the bases of both T1 and T2 to the down level...