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Browse Prior Art Database

Three Device FET Cell

IP.com Disclosure Number: IPCOM000074880D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Zehle, AM: AUTHOR

Abstract

Three-device FET memory cells are greatly improved by the efficient use of the parasitic overlap capacitances C-1 and C-2 shown in Fig. A. By proper layout, the tracking between C-1 and C-2 can be maintained exactly. This tracking is achieved by the layout shown in Fig. B which reduces the cell area, increases storage capacitance and permits operation and lower drive voltages. Capacitive tracking is provided by leaving a region 12 in device T1, which exposes the thinner oxide 13 and permits room for mask misalignment during metal deposition over the drain region 15.

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Three Device FET Cell

Three-device FET memory cells are greatly improved by the efficient use of the parasitic overlap capacitances C-1 and C-2 shown in Fig. A. By proper layout, the tracking between C-1 and C-2 can be maintained exactly. This tracking is achieved by the layout shown in Fig. B which reduces the cell area, increases storage capacitance and permits operation and lower drive voltages. Capacitive tracking is provided by leaving a region 12 in device T1, which exposes the thinner oxide 13 and permits room for mask misalignment during metal deposition over the drain region 15. Similarly, in device T3, the metal is arranged to leave exposed a corner region 14 of the overlap of the thin oxide 16 on the source 17 of device T3; thus, in case of misalignment of the metal deposition mask, movement of the mask in any direction causes the capacitance of both T1 and T3 to maintain the same ratios.

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