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Diagnostic Time Delay Recorder

IP.com Disclosure Number: IPCOM000074889D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Martin, DB: AUTHOR

Abstract

Time-delay intervals in the range of 0.1 to 120 seconds can be recorded graphically against real time with the illustrated arrangement of a banking terminal 1, voltage ramp generator 2, and strip recorder 3.

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Diagnostic Time Delay Recorder

Time-delay intervals in the range of 0.1 to 120 seconds can be recorded graphically against real time with the illustrated arrangement of a banking terminal 1, voltage ramp generator 2, and strip recorder 3.

Control signal 4 is representative of a time-delay interval T1 between a request for, and a provision of, service at terminal 1. Interval T1 of control signal 4 is translated by generator 2 into height V1 of voltage ramp 5. For a longer interval T2 (shown in dotted outline), ramp 5 has a proportionately greater height V2 (dotted) but the same slope as for interval T1.

At the beginning of interval T1, the level of signal 4 drops to zero, thereby cutting off current from diode D to the gate of MOSFET 2a. Consequently, the voltage rises at the drain of MOSFET 2a, causing a charging current through capacitor C and resistor R. The voltage drop across resistor R is applied to the gate of highly sensitive MOSFET 2a. This feedback to the gate maintains the rise of voltage ramp 5 at the MOSFET drain. By choosing capacitor C and resistor R for a sufficiently large time constant RC, linearity of ramp 5 is ensured over time- delay intervals in the range of 0.1 to 120 seconds. At the end of interval T1, current from diode D switches MOSFET 2a into saturation, thus causing ramp 5 to drop to its reference level.

Strip recorder 3 converts each voltage ramp 5 into a lateral excursion of a pen over the surface of a slowly moving paper strip 6 to...