Browse Prior Art Database

Self Restoring Four Device FET Memory Cell

IP.com Disclosure Number: IPCOM000074893D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Scheerer, W: AUTHOR [+2]

Abstract

This nondestructive read-out memory cell for integrated technology consists of four field-effect transistors and is designed so that the written information is not destroyed after the cell has been in the standby state for a long period of time.

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Self Restoring Four Device FET Memory Cell

This nondestructive read-out memory cell for integrated technology consists of four field-effect transistors and is designed so that the written information is not destroyed after the cell has been in the standby state for a long period of time.

The two FET's Q2 and Q3 form the bistable multivibrator cell. The other two FET's Q1 and Q2 are employed as a control means and are connected to a word line WL via their gate electrodes, to bit lines 80 and B1 via their drain electrodes, and to nodes N1 and N2 via their source electrodes.

In the stand-by state of the cell, leakage currents cause a discharge in the cell capacities on nodes N1 and N2, so that the information stored in the cell is erased after a certain period of time. This loss of information is avoided by a suitably chosen recharging current being continuously applied to nodes N1 and N2 via an additional line VL and two high-resistance resistors R. To this end, the additional line VL is arranged on the surface of the dielectric covering the monolithic cell. At the crossings of this line with nodes N1 and N2, the dielectric is made conductive by doping, subsequently acting as an integrated resistor R.

The additional line VL may be omitted where recharging is effected through the existing word line WL. In the latter case the dielectric must be rendered conductive at the crossings of the word line with nodes N1 and N2.

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