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Dynamic Shift Register

IP.com Disclosure Number: IPCOM000074895D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Berger, H: AUTHOR [+2]

Abstract

The dynamic shift register shown consists of an inverter chain comprising inverted transistors which are pulsed via lateral PNP transistors in 2 phase operation. In this layout the base of the NPN transistor is identical to the collector of the PNP transistor and the collector of the NPN transistor of the base of the PNP transistor. Information, when being shifted, is temporarily stored in the capacities located between connecting points B, C, D, etc. and the n-region. The length of shifting pulses M1, M2 must be such that during a pulse of 0 these points are prevented from being charged to a full base emitter forward voltage. Only the second pulse supplements the charge to the forward voltage value, unless the preceding stage is set on at that time, redischarging the connecting point.

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Dynamic Shift Register

The dynamic shift register shown consists of an inverter chain comprising inverted transistors which are pulsed via lateral PNP transistors in 2 phase operation. In this layout the base of the NPN transistor is identical to the collector of the PNP transistor and the collector of the NPN transistor of the base of the PNP transistor. Information, when being shifted, is temporarily stored in the capacities located between connecting points B, C, D, etc. and the n-region. The length of shifting pulses M1, M2 must be such that during a pulse of 0 these points are prevented from being charged to a full base emitter forward voltage. Only the second pulse supplements the charge to the forward voltage value, unless the preceding stage is set on at that time, redischarging the connecting point. When a set on and set off transistor is associated with a logic 1 and logic 0, respectively, the information is inverted in each register stage and shifted. This solution has the advantage that no isolation diffusions are required between the individual transistors, thus ensuring high-packing density.

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