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Antisaturation TTL Circuit

IP.com Disclosure Number: IPCOM000074908D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Varada Rajan, HD: AUTHOR

Abstract

Figure 1 shows the basic circuit of a 2-input TTL gate. The output transistor Q2 is heavily saturated in its conducting state, and there can be a considerable desaturation delay in switching Q2 from the ON condition to the OFF condition. This deep saturation of Q2 can be eliminated by the approach shown in Fig. 2.

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Antisaturation TTL Circuit

Figure 1 shows the basic circuit of a 2-input TTL gate. The output transistor Q2 is heavily saturated in its conducting state, and there can be a considerable desaturation delay in switching Q2 from the ON condition to the OFF condition. This deep saturation of Q2 can be eliminated by the approach shown in Fig. 2.

In Fig. 2, R2/R3 is a tapped resistor connected between the base and collector of Q1. This restricts the degree of saturation of Q1 when the input is DOWN, and corresponds to the resistor R in Fig. 1. Q3 is employed to clamp the collector of Q2 at a desired level in the ON state and divert the excess base current to its collector. The tapping point A can be chosen as desired and this fixes the collector clamping potential (e.g. 0.2V), the drop across P2+R3 being easily defined in terms of R1.

Thus, Q2 is operated with its full beta realized, resulting in zero delay due to storage in the device during turn-off. Also, the effect of spreads in the value of beta of Q2 is minimized because of the large feedback by Q3. Furthermore, in integrated form the collector of Q3 can be in common with that of Q1, leading to only a small increase in area on the chip.

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