Browse Prior Art Database

FET Bipolar Integration

IP.com Disclosure Number: IPCOM000074919D
Original Publication Date: 1971-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Chang, IF: AUTHOR

Abstract

These methods provide integrated circuits including field-effect transistor devices and bipolar devices on a single substrate.

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FET Bipolar Integration

These methods provide integrated circuits including field-effect transistor devices and bipolar devices on a single substrate.

Shown in Fig. A is an integrated circuit structure containing a silicon gate FET, a bipolar transistor (or junction FET, see Fig. B below) and a diode. On substrate 1 (p-type) shown as an example) an initial thick oxide 2 is grown which will subsequently provide isolation between devices. The next steps are definition, diffusion and drive in of n-type pockets 3 and 4. The FET area is then defined and gate oxide 5 is grown. Excess oxide is removed from over pockets 3 and 4 and followed by epitaxial growth of n-type silicon areas 6, 7, 8 and 9 over the substrate. Silicon is selectively removed to define source (S), drain (D) and collector (C). Oxide layer 10 is provided to act as a diffusion mask for the next diffusion. Diffusion windows are defined and n-type impurity is diffused and driven in providing regions 11. Depending upon whether or not the oxide over gate 6 is removed, two different threshold silicon gate devices may be produced on the same substrate. This step may also determine the conductivity type of conductive land 9. Contact holes are defined and metallurgy, not shown, is applied.

Two different types of MOSFET devices and a junction FET may also be be fabricated along with bipolar devices by a similar process as shown in Fig. B. After diffusion of pockets 3 and 4 the FET area is not defined but excess...