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Single Masking for Emitter Base Diffusions

IP.com Disclosure Number: IPCOM000074942D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Oberai, AS: AUTHOR

Abstract

This masking technique eliminates the criticality of mask alignment between the emitter and the base contacts of a transistor by the use of a single mask to define the emitter and the base contacts.

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Single Masking for Emitter Base Diffusions

This masking technique eliminates the criticality of mask alignment between the emitter and the base contacts of a transistor by the use of a single mask to define the emitter and the base contacts.

Semiconductor wafer 10, typically silicon, has deposited thereon a layer of silicon dioxide 12, in which an opening 14 is made to permit a base diffusion 16. During the base diffusion or subsequent to it, a thin layer of oxide 18 is deposited in the opening 14. A layer of silicon nitride 20 is formed over the entire surface of the wafer. A layer of pyrolytically deposited silicon dioxide 22 is formed over the silicon nitride. The SiO(2) layer 22 is etched to establish openings 34 and 30, the former (34) being for the emitter diffusion and contact, and the latter two being for the base contacts. Photoresist layer 24 is restored and area 26, which is somewhat larger than the emitter hole size, is developed in the photoresist layer
24. Silicon nitride in opening 34 can now be etched through holes defined in SiO(2) layer 22. As silicon nitride etch does not etch SiO(2), the SiO(2) layer 22 can be utilized as a mask for etching silicon nitride. The remaining SiO(2) underneath the silicon nitride is etched by buffered HF and emitter diffusion can now proceed. Photoresist is reapplied except in the areas of openings 30. Openings are provided in the photoresist larger than openings 30. These openings permit the silicon nitride to be...