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Shifter Circuit

IP.com Disclosure Number: IPCOM000074962D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Bodendorf, DJ: AUTHOR [+2]

Abstract

This shifter circuit is capable of shifting data n-positions to the left or right (n = 0, 1 ....) within one CPU cycle.

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Shifter Circuit

This shifter circuit is capable of shifting data n-positions to the left or right (n = 0, 1 ....) within one CPU cycle.

A schematic circuit of the shifter is shown in Fig. 1. A logical representation of the shifter is shown in Fig. 2.

Figs. 3 and 4 show the circuit connections and pertinent waveforms.

The operation of the shifter is explained as follows: The "data-N to left" is connected to the n-th position to the right for a left shift operation and the "data-N to right" is connected to the n-th position to the left for a right shift. The "SL-N" or "SR-N" inputs are to control the number of positions of shifting left or right, respectively. The "SL-set" or "SR-reset" inputs are used to precondition the shifter before data is gated into the shifter. The "0" is the output for a left shift and the "0" is the output for a right shift. Example: Shifting left n-positions (SL- N). A negative pulse is applied at the SL-set input to precondition the shifter. Data is then gated into the shifter (at n-positions to the right) and will be shifted n- positions to the left when a positive pulse is applied at the SL-N.

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