Browse Prior Art Database

Polarity Hold Circuit with True and Complement Output

IP.com Disclosure Number: IPCOM000074963D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Bodendorf, DJ: AUTHOR [+2]

Abstract

This polarity hold circuit has both true and complement outputs and can be fabricated with fewer components than most equivalent circuits which provide the same functions. A schematic of the polarity hold circuit is shown in Fig. 1. The voltage waveforms are shown in Fig. 2. Its operation and waveform are described as follows: The clock is normally down. Raising the clock will result in setting the in-phase output (0) to the value of the data. When the clock is down, the circuit is insensitive to changes on the data line. T(B) and TC comprise the flip-flop stage in the circuit, while T(A) and T(D) serve mainly as buffer stages between the flip-flop and the output of the polarity hold circuit.

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Polarity Hold Circuit with True and Complement Output

This polarity hold circuit has both true and complement outputs and can be fabricated with fewer components than most equivalent circuits which provide the same functions. A schematic of the polarity hold circuit is shown in Fig. 1. The voltage waveforms are shown in Fig. 2. Its operation and waveform are described as follows: The clock is normally down. Raising the clock will result in setting the in-phase output (0) to the value of the data. When the clock is down, the circuit is insensitive to changes on the data line. T(B) and TC comprise the flip-flop stage in the circuit, while T(A) and T(D) serve mainly as buffer stages between the flip-flop and the output of the polarity hold circuit. D(F) and D(G) (regular PN junction diodes or Schottky diodes) are to provide an additional voltage drop to insure that only one side of the output buffer transistor is biased on and the other side of the output transistor is biased off. T(E) is the control gate for setting the polarity circuit, i.e., a high potential at the clock and a low potential at the data will turn on T(A) (0), if the clock and the data are both high. Then T(D) will turn on (0). R(CC) and D(X) are added to the circuit to reduce the loading of the driver circuit and increase the noise sensitivity of the circuit.

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