Browse Prior Art Database

High Speed Pointer

IP.com Disclosure Number: IPCOM000074981D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 68K

Publishing Venue

IBM

Related People

Cartman, FP: AUTHOR [+2]

Abstract

In a multiprocessor system in which the various processing elements and memory elements are interconnected with a crosspoint switch and the systems operate as in the article by B. C. Fox et al in the IBM Technical Disclosure Bulletin Vol. 13, No. 2, July, 1970, pages 580-582, a queue of service requests for a particular memory by a number of processing elements may arise. An alternative to the sequential scanning techniques described in the reference will be described. This alternative technique has the advantage that successive request selections can be performed quickly and at a constant rate.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

High Speed Pointer

In a multiprocessor system in which the various processing elements and memory elements are interconnected with a crosspoint switch and the systems operate as in the article by B. C. Fox et al in the IBM Technical Disclosure Bulletin Vol. 13, No. 2, July, 1970, pages 580-582, a queue of service requests for a particular memory by a number of processing elements may arise. An alternative to the sequential scanning techniques described in the reference will be described. This alternative technique has the advantage that successive request selections can be performed quickly and at a constant rate.

Fig. 1 contains an overview of a selection system (High Speed Pointer) serving 64 successively ranked processors E0-E63 and n+1 memory units Mo- Mn. The objective of the mechanism is to select from among the active processor requests for memory connections, the one originated by the processor ranked next higher to the last serviced processor. When a memory is ready to service a new request, clock 1 is issued to latch all the active input requests in request latches 101 and OR them in octal groups R0-R7 (Fig. 2).

Immediately thereafter, in intervals defined by clocks 2 and 3, pointer selection logic 102 (Fig. 1) is operated to effect selection and setting of one of the 65 pointer latches 103. Ordinarily therefore, at clock 1 time, a single one of the 65 pointer latches will manifest a set condition and the other pointer latches will hold reset conditions. The 64 pointer latch conditions p0-p63 are also OR'd in octal groups Fig. 2) providing respective group pointer indications P0-P7. The latch providing indication pS is set Fig. 3) at start of request service operations, or whenever there are no pending processor requests for connection and a memory unit is available.

The pointer latch which holds the set condition is utilized after clock 4 time to "close" an appropriate crosspoint in connection matrix 10...