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Pattern Generating System

IP.com Disclosure Number: IPCOM000075006D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Legnard, E: AUTHOR [+3]

Abstract

Functional testing of metal oxide semiconductor devices requires a wide range of input test rates, a large number of controlled operations and a storage capacity for test patterns in expected outputs. Computer control and computer memory reduces the speed of operation. To achieve data pattern inputs and outputs in excess of two MHz for functional testing, data storage using dynamic devices are required. However, for a generalized programmable functional tester such dynamic devices limit system capability.

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Pattern Generating System

Functional testing of metal oxide semiconductor devices requires a wide range of input test rates, a large number of controlled operations and a storage capacity for test patterns in expected outputs. Computer control and computer memory reduces the speed of operation. To achieve data pattern inputs and outputs in excess of two MHz for functional testing, data storage using dynamic devices are required. However, for a generalized programmable functional tester such dynamic devices limit system capability.

This pattern generating system provides outputs of write, read and data at real-time cycles up to 10 MHz. The pattern generating system block diagram is shown in Fig. 1. Selected patterns comprised of eight word groups are stored in a solid state memory 10 whose output is double-buffered by first introducing the information into an eight word buffer register 11, and then introducing it on demand into a second eight word buffer register 12. Register 12 contains the information necessary for generating the present pattern, while register 11 contains the information for the next successive pattern.

Coupled to the second buffer memory 12 is an eight-position register ring 13 gated by a cycle clock 14 whose frequency can be varied.

Each group of eight words in a buffer register can be considered a pattern; or, more than one group of eight words can be linked together to form a pattern. Such words are illustrated in Fig. 2. An end of pattern is designated by a "one" state in bit position 1 of word 4. When the last of a particular pattern is run, an end of test is indicated by bit position 4 of register 4.

Start-up of the generator is accomplished by presetting an address in the memory address register 15, coupled to the memory 10; and, giving a start command. The first group of eight words is then transferred from the memory 10 to buffer 11 and then to buffer 12. In buffer 12 the first bit of the fourth word is interrogated. If it is in the ""one'' state, the next group of eight words will start from the address in memory 10, indicated by the address preset section of word
2. If it is in the "zero" state, then the next group of eight words will come sequentially.

Word 1 contains write and data information. Thus if a write "one" operation were decided in the first cycle, a "one" would be written into the first bit position under write and data. The second word contains read and preset information....