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Random Access Potential Ramp Memory for Charge Coupled Devices

IP.com Disclosure Number: IPCOM000075007D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Heller, L: AUTHOR [+4]

Abstract

A random access potential ramp memory can be created to sense the full amount of charge stored in a random access semiconductor charge-coupled device memory, despite the large parasitic capacitance associated therewith. This is accomplished by using a ramp potential surface charge transfer technique to provide write in and read out capabilities for a random access array of potential wells containing binary information, represented by the presence or absence of charge. This technique eliminates the need for diffusion within the memory array, increases density and provides increased detection capabilities.

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Random Access Potential Ramp Memory for Charge Coupled Devices

A random access potential ramp memory can be created to sense the full amount of charge stored in a random access semiconductor charge-coupled device memory, despite the large parasitic capacitance associated therewith. This is accomplished by using a ramp potential surface charge transfer technique to provide write in and read out capabilities for a random access array of potential wells containing binary information, represented by the presence or absence of charge. This technique eliminates the need for diffusion within the memory array, increases density and provides increased detection capabilities.

Fig. 1 shows a semiconductor body 10 having a thin oxide layer 11 on its upper surface. Overlying layer 11 is a first conductive line 12, biased by power supply 13.

A resistive line 15 is deposited over oxide layer 11 parallel and adjacent to conductive line 12. Both conductive line 12 and resistive line 15 are coated with a thick oxide layer 16 which insulates a second conductive line 17, crossing lines 12 and 15 at right angles, from lines 12 and 15. Disposed at one end of line 15 is a gate electrode 18 and a diffusion 19, which coact with a suitable circuit 20 to detect the presence or absence of charge under line 15. Circuit 20 also serves to properly bias the gate electrode 18 and the diffusion 19, and to provide an output 21 or a signal to a voltage source 22 which applies a suitable bias to the resistive line 15.

The memory operates as follows: conductive line 12 is biased, by source 13, to a level sufficient to create in the semiconductor body 10 a depletion region 23. This depletion region, shown in Fig. 2, is capable of storing minority charges. For convenience, the presence of such charges in region 23 will be considered a "1" in binary language and the absence of charge a "0". Resistive line 15 is now biased by source 22 such that a graded pote...