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Gated J K Flip Flop

IP.com Disclosure Number: IPCOM000075011D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Maholick, AW: AUTHOR

Abstract

A J-K flip-flop is a multistate circuit having two inputs, each input when energized setting the flip-flop to a corresponding stable output state, which will be held after the energization is removed. If both inputs are simultaneously energized, the flip-flop will change from whatever state it is in to the opposite state. Unless both inputs are simultaneously de-energized, the flip-flop output will be left at the state corresponding to the last energized input. A clock or gate input will allow the control inputs to be effective only when the clock input is energized.

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Gated J K Flip Flop

A J-K flip-flop is a multistate circuit having two inputs, each input when energized setting the flip-flop to a corresponding stable output state, which will be held after the energization is removed. If both inputs are simultaneously energized, the flip-flop will change from whatever state it is in to the opposite state. Unless both inputs are simultaneously de-energized, the flip-flop output will be left at the state corresponding to the last energized input. A clock or gate input will allow the control inputs to be effective only when the clock input is energized.

In the figure; three pairs of AND-In ERT circuits 1 and 2, 3 and 4, and 5 and 6 are each cross-connected to have the output of each of the pairs as an input to the other of the pairs. The output 11 of circuit 1 is also an input of circuit 3 and the output 12 of circuit 2 is an input of circuit 4. The output 13 of circuit 3 is connected as an input of both circuits 1 and 6 in addition to circuit 4, while the output 14 of the block 4 is similarly connected as an input to circuits 2, 3 and 5. The output of circuit 5 is energized as the "set" output of the flip-flop and is fed back as an input of circuit 2 and similarly, the output of circuit 6 when energized, is the "reset" output and is fed back as an input to circuit 1.

A normally energized input 20 to circuit 5 can be de-energized at when the clock input 24 is not energized to "set" the flip-flop, and a normally energized input 21...