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Testing of Linear Feedback Shift Registers

IP.com Disclosure Number: IPCOM000075034D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Bossen, DC: AUTHOR [+2]

Abstract

A method of obtaining test sequences for linear feedback shift registers is provided in which the technique gives predictable coverage for both Exclusive-OR portions and latch portions of the network. A set of test patterns has been derived for the 16-stage cyclic redundancy check (CRC) shift register. The testing begins by having the CRC register reset to all 0's. Next, two bytes of all (b(1) and b(2)) 0's are entered into the register followed by two more bytes (b(3) and b(4)) which set the register to the required initial state for the test sequence (b(5) through b(11)), which has been determined by the method given in "Test Patterns For Parity Networks" by D. C. Bossen, D. L. Ostapko, and A. M. Patel in the IBM Technical Disclosure Bulletin Volume 13, No.

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Testing of Linear Feedback Shift Registers

A method of obtaining test sequences for linear feedback shift registers is provided in which the technique gives predictable coverage for both Exclusive- OR portions and latch portions of the network. A set of test patterns has been derived for the 16-stage cyclic redundancy check (CRC) shift register. The testing begins by having the CRC register reset to all 0's. Next, two bytes of all (b(1) and b(2)) 0's are entered into the register followed by two more bytes (b(3) and b(4)) which set the register to the required initial state for the test sequence (b(5) through b(11)), which has been determined by the method given in "Test Patterns For Parity Networks" by D. C. Bossen, D. L. Ostapko, and A. M. Patel in the IBM Technical Disclosure Bulletin Volume 13, No. 10, March, 1971, Pages 2897-2899, using the fact that a feedback shift register is a sequence processor. These test sequences are shown in Table 1.

After b(11) has been entered, the two CRC characters CR(1) and CR(2) are shifted out of the register. The entire set of bytes b(1), b(2),...,b(11), CR(1),CR(2) is written on tape. During the subsequent reading of this record, CR(1) and CR(2) as written on the tape should be compared with the 2 CRC characters being generated during the reading.

The complete set of test bytes is shown in Table 1 for the particular 16-stage parallel linear feedback shift register shown in the figure.

(Image Omitted)

From a theoretical standpoint, the ability to test a linear feedback shift register results from a number of im...