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Method of Testing Circuits

IP.com Disclosure Number: IPCOM000075038D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Singh, S: AUTHOR [+2]

Abstract

This is a method of testing circuit chips using untested chips as a standard. A portion, typically seven, of the untested chip group comprising a hundred chips, is selected at random and used as a reference standard. A random pulse generator 10 generates through input lines 12 patterns of pulses. These pulses are applied to the test standard chips, grouped in parallel in the reference module 16, and also fed successively to each of the ninety-three remaining chips 18 by the input leads 17. Input lines 12 transmit to each of the untested chips, a plurality of input signals desired from the random pulse generator 10. Each of the untested chips is provided with an output line leading to a majority logic gate having an output lead 15.

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Method of Testing Circuits

This is a method of testing circuit chips using untested chips as a standard.

A portion, typically seven, of the untested chip group comprising a hundred chips, is selected at random and used as a reference standard. A random pulse generator 10 generates through input lines 12 patterns of pulses. These pulses are applied to the test standard chips, grouped in parallel in the reference module 16, and also fed successively to each of the ninety-three remaining chips 18 by the input leads 17. Input lines 12 transmit to each of the untested chips, a plurality of input signals desired from the random pulse generator 10. Each of the untested chips is provided with an output line leading to a majority logic gate having an output lead 15. Both the untested chips station and the majority logic gate are included in the reference module 16. The majority logic gate is employed to determine the majority outputs of the test standard chips. Each majority output is compared with the respective outputs of the remaining chips, to determine which of the latter are qualified. The output lead 19 of each circuit chip 18 is fed, along with the output 15 of reference module 16, to an Exclusive OR circuit 20 which acts as a comparator to determine whether the signals at output leads 15 and 19 are the same. The decision made by the Exclusive OR circuit 20 is provided at its output 21. If the circuit chip 18 provides the same output signal at 19 as the reference...