Browse Prior Art Database

Transformerless Bit Sense Line Multiplexer Magnetic Memory Device

IP.com Disclosure Number: IPCOM000075044D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Liebschutz, LC: AUTHOR [+2]

Abstract

A word organized memory comprises plural magnetic storage elements 10, consisting of a conductor substrate 11 and plural cylindrical uniaxial anisotropic magnetic films 12 superposed on the periphery of and along the A word organized memory comprises plural magnetic storage elements 10, consisting of a conductor substrate 11 and plural cylindrical uniaxial anisotropic magnetic films 12 superposed on the periphery of and along the length of the conductor substrate. The number of discrete magnetic films 12 is at least equal to the number of data bits of the data words being stored.

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Transformerless Bit Sense Line Multiplexer Magnetic Memory Device

A word organized memory comprises plural magnetic storage elements 10, consisting of a conductor substrate 11 and plural cylindrical uniaxial anisotropic magnetic films 12 superposed on the periphery of and along the A word organized memory comprises plural magnetic storage elements 10, consisting of a conductor substrate 11 and plural cylindrical uniaxial anisotropic magnetic films 12 superposed on the periphery of and along the length of the conductor substrate. The number of discrete magnetic films 12 is at least equal to the number of data bits of the data words being stored. In a word organized memory, the conductor substrate 11 functions as the word line and the film bits 12 are oriented with a closed hard 15, 16, and 17 arranged in pairs on opposite sides of the storage elements 10 with electrical connections 18, 19, and 20, formed as shown, to effectively make one continuous two-turn coil. In a practical embodiment, the bit line conductors 14-17 are thin printed circuit conductor layers formed on a flexible dielectric substrate which are superimposed to overlay the storage elements 10 in a laminated construction, and the conductor connections 18-20 between the conductor layers are formed by plated-through holes, or the like.

In a multiplexing network, the two-turn bit/sense lines 13 are connected across resistors R0 into individual multiplexing channels through Read Diodes to a common sense amplifier 21. Channel selection is controlled by the E-switch circuits S1-SN which essentially comprise high-power logic gates. The individual E-switches S1-SN are connected to the lead wire by the E-switch circuits S1-SN which essentially comprise high-power logic gates. The individual E-switches S1- SN are connected to the lead wire 20 of the two-turn strap, as shown in Fig. 1. In the read mode, the selected channel E-switch circuit output voltage is set to a Down level (near 0 volts) and the remaining unselected E-switches are set to Up levels (+ V(EE) or greater). This causes the pair of read diodes in the selec...