Browse Prior Art Database

FET Time Delay Pulse Generator

IP.com Disclosure Number: IPCOM000075057D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 22K

Publishing Venue

IBM

Related People

Donofrio, NM: AUTHOR [+2]

Abstract

This circuit establishes a fixed time delay from input to output that can be set independently of the load being driven.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

FET Time Delay Pulse Generator

This circuit establishes a fixed time delay from input to output that can be set independently of the load being driven.

The restore pulse R is applied to the gate of device Q3 to discharge node B to ground. When this happens, polarized capacitor CD is charged in the indicated polarity to the potential VB. The chip select pulse CS is complementary to the restore pulse R, so that CS begins to rise as R starts to fall to ground potential. Node A, therefore, begins to rise. As node A rises, device Q2 conducts causing node B to rise and thereby produce a delayed chip select pulse CSD at the output of the circuit. The time delay between CS and CSD depends on the time constant required to reverse bias the capacitor :CD and thereby raise the potential at node B.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]