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Auto Reset Ternary Latch

IP.com Disclosure Number: IPCOM000075089D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Maley, GA: AUTHOR [+2]

Abstract

Input and output lines of this latch are adapted to assume any one of three potential levels. After being set, the latch does not have to be reset before being set again.

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Auto Reset Ternary Latch

Input and output lines of this latch are adapted to assume any one of three potential levels. After being set, the latch does not have to be reset before being set again.

OR 1 is provided with a Data input line and a Gate input line. The output of OR 1 is fed to the input of Interchanger 1 circuit 2.

OR 3 is provided with an input extending from the gate line and input 5 provided from the output of circuit 2. The output of OR 3 goes to the input of Interchanger 1 circuit 4. Within dashed lines 6, there is shown a ternary latch. Set line 7 of latch 6 extends to one of the inputs of OR 9 having its output fed to the input of Interchanger 1 circuit 10. Reset line 8 of latch 6 extends to one of the inputs of OR 11 having its output fed to the input of Interchanger 1 circuit 12. Lead 13 extends from the output line to the other input of OR 11. Lead 14 extends from the output of circuit 12 to the other input line of OR 9.

The symbols and truth tables for the Interchanger 1 circuit and the OR function are shown.

Normally the gate line is at a "2" level and latch 6 is insensitive to all changes on the data line. However, if the gate line is lowered to a "0", latch 6 operates to match the value of data input and remains latched in this state as the gate line returns to "2". Latch 6 need not be reset before setting it to a new value. When the gate line is lowered only half way to a "1", the output line moves up or down only one level to an intermed...