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Three State Latch

IP.com Disclosure Number: IPCOM000075090D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Maley, GA: AUTHOR [+2]

Abstract

The three-state latch (Fig. 1) can store one ternary digit. It comprises two ternary OR circuits 1, 2, two Interchanger circuits 3, 4, an input set line 5, an output line 6, and a reset line 7. The individual logic blocks OR and INT perform logic functions as are shown in the truth tables (Figs. 2 and 3). The output line C of the OR circuit (Fig. 2) always assume the highest level applied to either of the input lines A, B. The interchanger circuit (Fig. 3) transforms low level "0" to high level "2" and vice versa, whereas intermediate level "1" is through passed from input line D to output line E.

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Three State Latch

The three-state latch (Fig. 1) can store one ternary digit. It comprises two ternary OR circuits 1, 2, two Interchanger circuits 3, 4, an input set line 5, an output line 6, and a reset line 7. The individual logic blocks OR and INT perform logic functions as are shown in the truth tables (Figs. 2 and 3). The output line C of the OR circuit (Fig. 2) always assume the highest level applied to either of the input lines A, B. The interchanger circuit (Fig. 3) transforms low level "0" to high level "2" and vice versa, whereas intermediate level "1" is through passed from input line D to output line E.

In the three-state latch (Fig. 1) the level of output line 6 follows that of input set line 5 as the level of the latter is raised from 0 through 1 to level 2. The level of output line 6 is held at the highest level reached by input set line 5 even if the level of line 5 is subsequently reduced. When the level of reset line 7 is raised from 0 through 1 to level 2, the level of output line 6 falls from 2 to 1 and back to the original level 0.

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