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Browse Prior Art Database

Floating Memory Cell

IP.com Disclosure Number: IPCOM000075102D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Broom, RF: AUTHOR [+2]

Abstract

This memory cell permits construction of large-scale integrated semiconductor memories that have no power distribution lines and no ground return lines crossing over the memory surface. The cell consists of Schottky gate field-effect transistors of the normally off-type. Stand-by power is supplied by a Schottky diode photovoltaic cell. Fig. 1 shows a simple cross-point switch with memory function. If the side with the double-drain transistor is conducting, a low ohmic path exists between bit and word line. When these lines are properly connected, a current can flow which is independent of the stand-by current of the cell. No current flows if either line is disconnected. To write a "0" into the well, a negative pulse is applied to the bit line. This renders the drain-gate diode of the double-drain transistor conductive.

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Floating Memory Cell

This memory cell permits construction of large-scale integrated semiconductor memories that have no power distribution lines and no ground return lines crossing over the memory surface. The cell consists of Schottky gate field-effect transistors of the normally off-type. Stand-by power is supplied by a Schottky diode photovoltaic cell. Fig. 1 shows a simple cross-point switch with memory function. If the side with the double-drain transistor is conducting, a low ohmic path exists between bit and word line. When these lines are properly connected, a current can flow which is independent of the stand-by current of the cell. No current flows if either line is disconnected. To write a "0" into the well, a negative pulse is applied to the bit line. This renders the drain-gate diode of the double-drain transistor conductive. Node A goes negative and the double-drain transistor is cutoff. To write "1" a positive pulse is applied which renders diode B conductive and drives node A positive, thereby switching on the double-drain transistor.

Fig. 2 shows a version of the same cell for a memory having two bit lines. Two double-drain transistors are used. Write-in occurs as indicated in the drawing, while readout is equivalent to that described above.

Note that readout current of the cell is independent of the stand-by current. Therefore, the switching speed is mainly influenced by the drive conditions on the bit and word lines and does not depend on the...