Browse Prior Art Database

Deserializer

IP.com Disclosure Number: IPCOM000075104D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Williams, C: AUTHOR

Abstract

Serial data consisting of a single-start bit S followed by a succession of nine-bit bytes is entered to the deserializer 1. The deserializer 1 consists of a shift register 2 and a shift-buffer 3. The shift buffer and register are initially reset to 0's.

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Deserializer

Serial data consisting of a single-start bit S followed by a succession of nine- bit bytes is entered to the deserializer 1. The deserializer 1 consists of a shift register 2 and a shift-buffer 3. The shift buffer and register are initially reset to 0's.

At clock 3 time, the bits in shift buffer 3 are set in shift register 2 shifted one place to the right. At clock 0 time the bits in shift register 2 are set in shift buffer
3. When the start bit S is shifted into bit S of the shift buffer 3, the first nine-bit byte is available for parallel transmission. At the next clock 2 time, AND gate 4 resets the shift buffer 3, except bit S to 0's. During the next clock 3 time, the start bit S from shift buffer 3 is set in bit 7 of shift register 2 using OR gate 5 at the same time as the first bit of the next byte is set in bit P of the shift register 2. This dummy start bit in bit 7 of the shift register is shifted to the right as successive bits are entered into the deserializer and when it reaches the S bit of buffer 3, a second byte is available for parallel transmission. This procedure is repeated for each further incoming byte.

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