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Error Correction System

IP.com Disclosure Number: IPCOM000075107D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Gerrand, F: AUTHOR [+3]

Abstract

In this SEC-DED code, for four-byte data entities, eight check bits are generated over the data bits when data is written into storage, according to the following equations: C1 = 1+2+3+4+5+6+7+8+14+19+25+31 C2 = 1+5+6+7+8+9+10+11+12+20+26+32 C3 = 2+8+9+10+11+12+13+14+15+16+21+27 C4 = 3+7+13+14+15+16+17+18+19+20+22+28 C5 = 4+10+15+17+18+19+20+21+22+23+24+29 C6 = 5+11+16+21+22+23+24+25+26r27+28+30 C7 = 6+12r17+23+25+26+27+28+29+30+31+32 C8 = 1+2+3+4+9+13+18+24+29+30+31+32. The check bits are stored along with the data bits. On a subsequent read cycle, the data and check bits are read from storage in parallel and eight parity bits are generated over data and check bits as in I.

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Error Correction System

In this SEC-DED code, for four-byte data entities, eight check bits are generated over the data bits when data is written into storage, according to the following equations: C1 = 1+2+3+4+5+6+7+8+14+19+25+31 C2 = 1+5+6+7+8+9+10+11+12+20+26+32 C3 = 2+8+9+10+11+12+13+14+15+16+21+27 C4 = 3+7+13+14+15+16+17+18+19+20+22+28 C5 = 4+10+15+17+18+19+20+21+22+23+24+29 C6 = 5+11+16+21+22+23+24+25+26r27+28+30 C7 = 6+12r17+23+25+26+27+28+29+30+31+32 C8 = 1+2+3+4+9+13+18+24+29+30+31+32. The check bits are stored along with the data bits. On a subsequent read cycle, the data and check bits are read from storage in parallel and eight parity bits are generated over data and check bits as in I.

If a single error occurs, the group of eight parity bits can be interrogated in groups of three to locate the error, since a unique three of the eight bits covers each data bit.

Thus, each data bit can be corrected during the same read cycle. For example, and as in I, if P1, P2, and P3 are each 1, any single error which occurs is in data bit 8. Correction for this bit is accomplished as in II. If P1, P2, and P3 activate And 1, an output is produced on line 3. Uncorrected data bit 8 is transmitted on line 5. Exclusive-Or 7 then inverts data bit 8 to produce corrected data bit 8. If, on the other hand, P1, P2 and P3 are not 1, bit 8 is correct as read. Therefore, line 3 is inactive and Exclusive-Or 7 does not invert data bit 8. Each data bit is similarly corrected in parallel.

Single errors can be discriminated from double errors, as in III. Each parity bit is connected to Or 9 and Exclusive-Or 15. Output 11 of Or 9 is connected to And
13. Output 17 of Exclusive-Or 15, which is active when an even number of parity bits are 1, is connected as a second input to And 13. Output 19 of Exclusive-Or 15 is active when an odd number of parity bits are 1. In operation on a given read cycle, an odd number of parity bits active indicates a single error on line 19. If line 17 is active, there is an even number of parity bits active. If the even number is other than zero, the parity coverage insures detection of a dou...