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Browse Prior Art Database

Test for Read Only Memories

IP.com Disclosure Number: IPCOM000075123D
Original Publication Date: 1971-Aug-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Falconer, JH: AUTHOR [+2]

Abstract

This is a method of testing ROMs (Read-Only Memory) that eliminates the need for comparing the entire contents (M words by N bits) of a ROM under test with an M x N bit array test pattern.

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Test for Read Only Memories

This is a method of testing ROMs (Read-Only Memory) that eliminates the need for comparing the entire contents (M words by N bits) of a ROM under test with an M x N bit array test pattern.

The contents of ROM UNDER TEST 1 is considered to be a stream of M x N bits. Address register 3 applies M addresses to ROM 1 at a selected test frequency rate.

Every address of ROM 1 for each output #1, #2..., #N is selected sequentially by N-bit shift register 4 at Data Selector Block 5. The output from Block 5, i.e., a stream of M x N bits, is shifted serially into accumulator 6.

Accumulator 6 is a P-bit shift register having multiple feedback paths. A register of this type is described by Hsiao, et al, in IEEE Transactions on Electronic Computers, December 1964, at 738-740. The transfer of the ROM bit stream into accumulator 6 effectively divides the bit stream, a polynomial of degree M x N, by a polynomial of degree P, thereby generating a P-bit remainder.

The P-bit remainder contained in accumulator 6 after the entire M x N bits have been accumulated is compared at comparator 7 with the expected P-bit pattern generated by a simulation technique.

ROM 1 is acceptable only if there is a perfect match between the generated pattern and the expected pattern. The length and the feedback arrangement of accumulator 6 is selected to control the probability of accepting a bad ROM, reducing it to an acceptably low level.

The proper selection of a feedback-s...