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Low Inductance Transistor

IP.com Disclosure Number: IPCOM000075124D
Original Publication Date: 1971-Aug-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Hart, BE: AUTHOR [+2]

Abstract

This power transistor structure is designed to have low inductance useful for high-frequency transient conditions found in shunt regulator circuits in low-voltage high-current power supplies. The structure reduces inductance, particularly in the emitter circuit, thus increasing the useful frequency range, and provides a thermally stable emitter resistor which is substantially noninductive. The overall shape is adapted for convenient insertion into or in cooperation with a strip line power buss.

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Low Inductance Transistor

This power transistor structure is designed to have low inductance useful for high-frequency transient conditions found in shunt regulator circuits in low- voltage high-current power supplies. The structure reduces inductance, particularly in the emitter circuit, thus increasing the useful frequency range, and provides a thermally stable emitter resistor which is substantially noninductive. The overall shape is adapted for convenient insertion into or in cooperation with a strip line power buss.

The package includes a bottom plate 10, a top plate 12 and insulation 14 therebetween. Plate 10 is counter bored to form a chamber 16 having a circular pedestal portion 18. A molybdenum or tungsten disk 20 on 18 forms an electrical contact to the collector of the transistor, as well as a thermal contact for communicating heat from the transistor to plate 10 as a heat sink.

The transistor itself consists of a silicon wafer 22, the lower surface and body of which constitutes the collector of the transistor For an NPN transistor, wafer 20 is of N-type silicon having emitter areas in its upper surface and base areas between the emitter areas and the collector portions. Typically, the N-type body has P-doped regions infused into its upper surface to form the base regions, and N-type emitter regions infused into the top of the base regions. To provide access to the base, the emitter diffusion operation is selective, as by masking, or portions of the emitter layer are etched away, in either case leaving parts of the base portions exposed. Metallization 24 is deposited over the emitter portions and metallization 26 is deposited over the base portions. A contact ring 28 is placed over the rim portion of metallization 24 to form the emitter terminal.

Upper plate 12 is counter bored to provide an emitter cup 30...