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Phosphosilicate Glass and Underlay Passivation Method and Structure

IP.com Disclosure Number: IPCOM000075156D
Original Publication Date: 1971-Aug-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Corl, EA: AUTHOR [+2]

Abstract

This process provides a higher degree of quality and stability for phosphosilicate glass and underlay passivation layers associated with silicon semiconductor devices.

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Phosphosilicate Glass and Underlay Passivation Method and Structure

This process provides a higher degree of quality and stability for phosphosilicate glass and underlay passivation layers associated with silicon semiconductor devices.

In Fig. 1 a silicon dioxide layer 12 is formed on a silicon base 14 using conventional photolithographic techniques.

In Fig. 2, a phosphorous rich material followed by an underlay of pyrolytic oxide is deposited over the silicon dioxide layer to form layer 16.

In Fig. 3, a high-temperature bake operation is performed, which diffuses the phosphorous into the silicon base 14 so as to form diffused region 18. The high temperature baking step also creates a region of phosphosilicate glass across the wafer, but beneath the underlay.

By following this exact sequence of process steps, the following advantages result: Increased glass densification, minimal migration of phosphorous through the glass, even distribution of phosphorous through the underlay, and minimal contamination between the successive process steps.

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